The present invention relates generally to floating point processors, and, more particularly, to an enhanced internal floating point processor format for exponent mapping.
A binary floating point processor (“BFP”) typically has to support operands and results in multiple formats, for example, 64-bit double precision (“DP”) in IEEE coding, 32-bit single precision (“SP”) in IEEE coding, SP in 64-bit DP IEEE coding, or 32-bit SP in Graphics or Non-Java coding. State-of-the-art BFPs typically support mixed precision, i.e., the formats of each operand and the result are independent and can be different. To support all of these and other formats in an efficient manner, the BFP converts its operands during the unpacking stage into a special internal format, and after the final rounding stage the result is converted back into the instruction specific format. The entire computation inside the BFP core is mainly independent of the input and output formats. Of importance is the internal format that the exponents get recoded into. In order to represent all possible intermediate exponents, the internal exponent format of state-of-the-art BFPs usually has two more bits than the widest input exponent. For BFPs supporting DP inputs, this might be a 13-bit biased format which guarantees that all occurring exponents can be represented with positive numbers. Recoding the inputs into this format can be done with little hardware effort by replicating a few bits. The major drawback of the format is that for each supported result precision, overflow and underflow checking logic is required. More specifically, each result precision has a different constant to check against for the underflow check. Overflow checks are only needed in the final rounding step, but underflow checks are needed frequently throughout the various BFP stages and these checks are relatively timing critical (e.g., exponent computation, aligner shift amount, normalizer shift amount, rounder), which adds to the overall delay and area of the BFP.